Dynamic random access memories have come into widespread use for digital data storage due to the small cell size and resulting high density. The current trends in dynamic memory circuit development are toward lower supply voltages and smaller storage capacitors. However, these design trends lead to a reduction in the signal margin between high and low voltage states which are read from the storage capacitor. As the signal margin becomes smaller there is a greater probability that the data will be in error.
In view of the importance of signal margin in dynamic random access memories there exists a need for a method and apparatus for increasing the signal margin without significantly increasing the complexity and size of the memory circuit.